In recent years, serial data transmissions have been the mainstream in high speed data transmissions between devices. In a high speed serial data transmission between semiconductor devices, a serializer/deserializer (SerDes) is used to convert outgoing parallel data into serial data and convert incoming serial data into parallel data. Since attenuation in transmission lines is more serious at higher transmission speed, it is important to evaluate the waveform quality in the reception circuit of the SerDes circuitry.
An attenuated waveform in high speed transmission is received and recovered by a clock data recovery circuit (CDR) For clock data recovery, the embedded clock system and accompanying clock system are available.
In the embedded clock system, data is sent with clock information embedded therein. The clock data recovery circuit separates data and clock information in received data to recover the data.
In the accompanying clock system, in the reception circuit of the SerDes with data lanes and accompanying clock lanes, a clock having phase information extracted from the clock data recovery circuit of an accompanying clock lane is sent to a data lane to recover the clock for the data lane. In the accompanying clock lane system, a clock is transmitted simultaneously with high-speed serial data and distributed to each data lane to enable transmission and reception of high-speed serial data. Also, since skews (time lags) between data and clock signals do not occur, data can be received with reference to the accompanying clock. Furthermore, unlike the embedded clock system, in the accompanying clock system, the eye-opening margin can be measured while the clock data recovery circuit follows changes in the received data in the same way as in normal operation (namely, jitter components are included). Besides, since the accompanying clock signal always switches between 1 and 0, even if received data includes a succession of same signs, the data can be received according to a phase control signal from the clock data recovery circuit. SerDes circuitry including such a clock data recovery circuit of a clock lane is disclosed in JP-A No. 2003-017999.
One approach to evaluating the received data waveform quality is eye-opening margin measurement. In various serial data transmission systems, the eye-opening at the transmitting and receiving ends is defined (compliance eye diagrams). Eye-opening margin measurement is to a method in which all shifts of waveform signals are overlapped and timing margins and voltage margins are measured at a time according to eye-opening.
Generally the embedded clock system is used for eye-opening margin measurement. Data synchronized with a clock signal is transmitted through a transmission line and the clock signal is extracted from the received data by a clock data recovery circuit on the receiving circuit and the received data is recovered. JP-A No. 2007-060655 discloses an eye-opening margin measurement method according to this embedded clock system.